1. Field of the Invention
The present invention relates to a semiconductor device having a pn junction, and more particularly, a semiconductor device and a resistor having a structure where an insulative isolator is provided on a semiconductor film disposed on an insulative substrate on the opposite side to the substrate without making contact with the substrate.
2. Description of the Background Art
Proposals for a so-called SOI (Silicon On Insulator) structure have been made conventionally. FIG. 62 is a sectional view exemplifying a structure of a CMOS (Complementary Metal Oxide Semiconductor) transistor 200 having the SOI structure. A Pxe2x88x92 type semiconductor layer 20 is provided on an insulator 9, and an insulative isolator 40 is provided separately from the insulator 9 on a surface of the semiconductor layer 20 on the far side from the insulator 9. Such an isolator that is separated from the insulator and provided on the surface of the semiconductor film disposed on the insulator for isolating the surface of the semiconductor layer is hereinafter tentatively referred to as xe2x80x9cpartial isolatorxe2x80x9d.
N+ type source/drain layers 21 and 22 are provided in the semiconductor layer 20. These source/drain layers and a gate electrode 23 provided on the semiconductor layer 20 with a gate insulating film interposed therebetween constitute an NMOS transistor 2. Such an NMOS transistor having the SOI structure including the partial isolator is disclosed in xe2x80x9cBulk-Layout-Compatible 0.18 xcexcm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)xe2x80x9d (Y. Hirano et al., 1999 IEEE International SOI Conference, October 1999, pp.131-132), for example.
An Nxe2x88x92 type semiconductor layer 10 is further provided on the insulator 9. P+ type source/drain layers 11 and 12 provided in the semiconductor layer 10 and a gate electrode 13 provided on the semiconductor layer 10 with a gate insulating film interposed therebetween constitute a PMOS transistor 1.
The source/drain layer 22 extends through the semiconductor layer 20, and the source/drain layer 12 extends through the semiconductor layer 10 in the thickness direction, respectively, to divide the respective semiconductor layers 10 and 20 in a sectional view. There is a semiconductor layer 20t being a part of the semiconductor layer 20 and a semiconductor layer 10t being a part of the semiconductor layer 10 between the source/drain layers 12 and 22. The semiconductor layers 20t and 10t are adjacent to each other to form a pn junction J1 under the partial isolator 40, that is, between the partial isolator and the insulator 9. The pn junction J1 is positioned in the above-described manner when, for example, the pn junction J1 is formed at the stage of forming the semiconductor layers 10 and 20 before forming the partial isolator 40 and the partial isolator 40 is then formed on a boundary between the semiconductor layers 10 and 20.
In this way, semiconductor layers of conductivity types different from each other, i.e., p and n type semiconductor layers are formed as a semiconductor film having the SOI structure in a general LSI (Large Scale Integrated Circuit), and a MOS transistor and a bipolar transistor are formed using these semiconductor layers.
However, it is observed in the structure shown in FIG. 62 that the pn junction J1 positioned under the partial isolator 40 results in occurrence of an abnormal leakage current at the pn junction J1.
According to a first aspect of the present invention, a semiconductor device comprises: a substrate at least having an insulative surface; a semiconductor film provided on the surface of the substrate comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of a second conductivity type opposite to the first conductivity type and a fourth semiconductor layer of the second conductivity type having an impurity concentration lower than that of the third semiconductor layer; and an insulative isolator formed on a surface of the semiconductor film on the far side from the substrate, separately from the surface of the substrate. In the semiconductor device, the second and fourth semiconductor layers form a pn junction extending in the thickness direction of the semiconductor film, and a maximum value of a distance between the pn junction and a boundary between the isolator and the semiconductor film is not more than 2 xcexcm, when a direction from the boundary to the isolator along the surface of the substrate is taken as a positive direction.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the pn junction has a portion separated from the isolator.
According to a third aspect of present invention, in the semiconductor device of the second aspect, the portion of the pn junction separated from the isolator forms a semiconductor element.
According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, the first, second, fourth and third semiconductor layers are adjacent to each other in this order, and the first and third semiconductor layers function as a contact with respect to the pn junction.
According to a fifth aspect of the present invention, in the semiconductor device of the second aspect, the first, fourth, second and third semiconductor layers are adjacent to each other in this order, and the first and second semiconductor layers function as source/drain layers of MOS transistors having conductivity types different from each other, respectively.
According to a sixth aspect of the present invention, the semiconductor device of the second aspect further comprises a cover having an insulative surface in contact with the portion of the pn junction separated from the isolator.
According to a seventh aspect of the present invention, the semiconductor device of the fifth aspect further comprises a cover having an insulative surface in contact with the portion of the pn junction separated from the isolator.
According to an eighth aspect of the present invention, in the semiconductor device of the second aspect, the second semiconductor layer is provided in the fourth semiconductor layer, the first semiconductor layer includes a pair of first semiconductor layers being formed in the second semiconductor layer, and the pair of first semiconductor layers function as a contact with respect to the second semiconductor layer.
According to a ninth aspect of the present invention, a semiconductor device comprises: a substrate at least having an insulative surface; a semiconductor film provided on the surface of the substrate, having at least one pn junction extending in a thickness direction of the substrate, the at least one pn junction including a pn junction which is applied with voltage; and a metallic compound layer selectively formed on the semiconductor film, being a compound of the semiconductor film and metal. In the semiconductor device, a maximum value of a distance between at least the pn junction which is applied with voltage and a boundary between the metallic compound layer and the semiconductor film is not more than 2 xcexcm, when a direction from the boundary to the semiconductor film along the surface of the substrate is taken as a positive direction.
According to a tenth aspect of the present invention, the semiconductor device of the ninth aspect further comprises a mask provided on the at least one pn junction for preventing combination of the at least one pn junction with metal of the semiconductor film.
According to an eleventh aspect of the present invention, in the semiconductor device of the tenth aspect, the mask has the same structure as a gate of a MOS transistor to be formed on the semiconductor film in a thickness direction thereof.
According to a twelfth aspect of the present invention, a resistor comprises: a substrate at least having an insulative surface; a first semiconductor layer of a first conductivity type provided on the surface of the substrate; an insulative isolator formed on a surface of the first semiconductor film on the far side from the substrate, separately from the surface of the substrate; and a second semiconductor layer of a second conductivity type opposite to the first conductivity type formed in the first semiconductor layer, the second semiconductor layer forming a pn junction in conjunction with the first semiconductor layer, the pn junction extending from the surface of the first semiconductor layer to the surface of the substrate and being separated from the isolator.
According to a thirteenth aspect of the present invention, the resistor of the twelfth aspect further comprises a pair of third semiconductor layers of the second conductivity type formed in the second semiconductor layer, having an impurity concentration higher than that of the second semiconductor layer.
According to a fourteenth aspect of the present invention, the resistor of the thirteenth aspect further comprises a gate electrode covering the pn junction.
According to a fifteenth aspect of the present invention, the resistor of the thirteenth aspect further comprises a cover having an insulative surface in contact with the portion of the pn junction separated from the isolator.
According to a sixteenth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) providing on an insulator a pn junction formed by a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, the pn junction extending from surfaces of the first and second semiconductor layers to the insulator, and providing an insulative isolator on the surfaces of the first and second semiconductor layers on the far side from the insulator, separately from the pn junction and the insulator; (b) forming a pair of third semiconductor layers in the first semiconductor layer as first source/drain layers, the third semiconductor layers having the second conductivity type and an impurity concentration higher than that of the second semiconductor layer; (c) forming a pair of fourth semiconductor layers in the second semiconductor layer as second source/drain layers, the fourth semiconductor layers having the first conductivity type and an impurity concentration higher than that of the first semiconductor layer; and (d) forming an insulating film on the pn junction and a pair of the first and second source/drain layers.
According to a seventeenth aspect of the present invention, in the method of the sixteenth aspect, the insulating film is formed in the step of forming gate insulating films of MOS transistors of conductivity types different from each other, the MOS transistors each having the first and second source/drain layers.
According to an eighteenth aspect of the present invention, in the method of the sixteenth aspect, the insulating film is formed in the step of forming sidewalls of gate electrodes of MOS transistors of conductivity types different from each other, the MOS transistors each having the first and second source/drain layers.
According to a nineteenth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) providing on an insulator a pn junction formed by a first semiconductor layer and a second semiconductor layer of a conductivity type different from that of the first semiconductor layer, the pn junction extending from a surface of the first and second semiconductor layers to the insulator, and providing an insulative isolator on the surface of the first and second semiconductor layers on the far side from the insulator, separately from the insulator, the insulative isolator having an opening for exposing the pn junction; (b) forming a semiconductor element having a gate on the first semiconductor layer; (c) forming a mask which covers the pn junction at the opening and exposes at least part of the surface of the first and second semiconductor layers at the opening; and (d) combining the surface of the first and second semiconductor layers which is exposed with metal.
According to a twentieth aspect of the present invention, in the method of the nineteenth aspect, the steps (b) and (c) are performed by the same process.
In the semiconductor device according to the first or second aspect, the defect density is very low at a position not more than 2 xcexcm from the boundary between the isolator and the semiconductor film, or a position where the isolator is not formed. This allows great reduction of the leakage current at the pn junction formed at the position.
The semiconductor device according to the third aspect can improve the flexibility in layout of the semiconductor device.
In the semiconductor device according to the fourth aspect, a diode with reduced leakage current can be obtained.
In the semiconductor device according to the fifth aspect, a CMOS transistor with reduced leakage current can be obtained.
In the semiconductor device according to the sixth or seventh aspect, it is possible to prevent the second and fourth semiconductor layers from being silicided when siliciding the first and third semiconductor layers.
In the semiconductor device according to the eighth aspect, a resistor with reduced leakage current can be obtained.
In the semiconductor device according to the ninth aspect, the defect density is very low at a position not more than 2 xcexcm from the boundary between the metallic compound and the semiconductor film. This allows great reduction of the leakage current at the pn junction formed at the position.
In the semiconductor device according to the tenth aspect, the pn junction is prevented from being shorted.
In the semiconductor device according to the eleventh aspect, it is possible to improve flatness of the interlayer insulating film to be formed on the semiconductor layer.
In the resistor according to the twelfth to fourteenth aspects, the pn junction is formed separately from the isolator, and the third semiconductor layer functions as a contact with respect to the resistor formed by the second semiconductor layer. Therefore, a resistor with reduced leakage current can be obtained.
In the resistor according to the fifteenth aspect, the first and second semiconductor layers can be prevented from being shorted even with silicidation performed.
With the method according to the sixteenth aspect, the semiconductor device of the sixth aspect can be manufactured.
With the method according to the seventeenth or eighteenth aspect, the semiconductor device of the sixth aspect can be manufactured easily.
With the method according to the nineteenth aspect, the semiconductor device of the eleventh aspect can be manufactured.
With the method according to the twentieth aspect, the semiconductor device of the eleventh aspect can be manufactured.
Consequently, the present invention is directed to a semiconductor device for controlling where the pn junction is positioned and suppressing occurrence of the leakage current.